Someone please explain the G2 bus 8-bit simple-bus timing Referring to jj1odm's helpful research, I hooked up a Logicport logic analyzer (thanks to a recommendation of another user here - fantastic piece of hardware) and have been studying the DC's 8-bit addr / data flow. Below is what I'm seeing. If someone could confirm what I'm seeing is correct, it would be helpful. Also, note that on the UBE / Write, there's half of a cycle where the state changes. I'm only supposed to take the data value starting at the leading edge of the clock after -300ns, correct? Also, how long am I supposed to sample that state? Also, I'm not 100% up to speed on the wire-workings of data transfer. The IRQA line is only activated if the hardware connected to the G2 wants the DC to poll it? Thanks for your input / help. Greatly appreciated.
I thought I might bump this again now that we have some more people viewing this forum that are more hardware-oriented. I can't get my analyzer to capture data for the life of me. I don't know if I have it configured incorrectly or what, but it doesn't seem like it's capturing nearly the amount of data that should be going through. Below is a picture of my configuration. For testing something to ensure my setup is correct, I wired a DC modem up to the analyzer. I only tapped into into the 8 address lines, 8 data lines, MODEMCS, IRQA, write enable, read enable, reset and clock, which should be all that's needed for the simple 8-bit bus mode. In the analyzer program, when I start the DC up, it IMMEDIATELY recognizes the proper 25MHz output from the clock. I have my logic threshold set to 1.40V since the DC uses CMOS logic levels. The trigger is set to capture when MODEMCS and either the read / write enables are low.
