GameBoy Color - Overclock and Underclock with FPGA Hey, I managed to (finally) get this project working after a few good hours. Nothing special really. Just 2 wires and I forwarded the clock signal from the FPGA to the GameBoy. Check it out if you want on YouTube (Yes APE, I talk in it :thumbsup Overlock > http://youtu.be/hzSewBBzpnQ Underclock > http://www.youtube.com/watch?v=-Tt9X4Gx3f4 Be sure to subscribe for more videos as I progress... Its SEGA, not SAYGA :lol: Thanks.
Yes..? You make it sound like I have not already done projects for pics/atmels. Im sure if I wanted to look into FPGA I could do something "better" (i.e. more interesting or better use of an FPGA). I understand its your first project, but you dont see people posting blinking led projects here while they are learning do do actual interesting stuff. You could do what you have done with a replacement crystal... hence, waste of an FPGA...
That's better. What Bad_Ad84 is saying, is: 1) Good work 2) Keep going 3) The basics are basics and if everyone posted their first "Hello World" we'd be inundated. And besides, you don't need our approval.
Pretty much, just more diplomatic. To be fair, I've had "one of those days", so I apologise if I was a little off.
Also, not really a waste of anything, because well the FPGA can be reprogrammed heh... Good work though haunted, certainly more that I could do at this point.
Thank you and you are welcome ;-) Ah, I understand. No worries :thumbsup: Thanks! Hahaha, very true. Thank you very much. I really appreciate the support! --- Every design, is bringing my closer the the PS SD card.
I got it underclocked. Just going to make 2 buttons, lower and raise the MHz and display it on the 7-segments. It is really fun all this logic stuff ^_^
This isn't as trivial as a "hello world", that's typically wiring a switch or button to a LED. Without knowing anything about the implementation though it's hard to know whether to say "good job" since a decent implementation will be difficult; something like a binary counter driving an asynchronous multiplexer where select asynchronously decodes a 7-seg will be easy and a very poor and unreliable implementation. If you had time-division-multiplexed 7-segs, a debounced select switch and a synchronized clock output that never dips below I dunno, 120ns which would be a 50% overclock of 4.14 MHz, or better yet an output that settles on 50% duty cycle, that'd be a good job. Either way good job I guess, I didn't know you had it in you to even pull off a 7-seg decoder. Maybe you should look into using the FPGA's PLL to get a 200 MHz input clock (5 ns period), which would drive a down-counter which toggles the output clock register (and reloads its value) on underflow. Operating the counter at 200 MHz means the output can toggle at up to 100 MHz or as low as a period of 10 ns. By having your frequency select mechanism load the counter you'll allow the user to change the frequency with 10 ns precision (it should be limited to a safe range). Also learning this circuit will be an important step to understanding audio synthesis. Operate one of these periodic counters at audible frequency and you'll have the world's worst "sound chip".
Uh, thanks Calpis. I was going to use a PLL line on the Cyclone II but I dont know how at the moment. I just used a 16 bit counter to basically divide the 24 MHz clock to give me multiple outputs of speed by adjusting the register's. The seven segment decoder is easy. There is just a single IC that does all the work for you really. Oh, the easiest way to get a 50% cycle I think, is to implement a process that divides the final output to the GameBoy by 2. When it comes to the PlayStation, I dont stop at anything to make my dream come true.
This is cool, don't listen to that hater Bad_Ad84. The short version of what Calpis is saying is use a fast clock on a counter and have your "clock speed select" change the value that gets reloaded when the counter reaches 0. You have a 50 MHz clock on board if that's a Terasic board which is plenty fast for now. Don't bother with the PLL just yet.
You mean /2, /4, /8, /16, /32? I strongly suggest learning gate level design too, not just HDL. HDL is a time saver for people already familiar with gate design, if you just jump into HDL I guess you can do some things but they probably won't be the "right way". lol then you aren't decoding! the IC is the 7-seg decoder >_< Sure, if the input clock has 50% duty cycle and you want /2... If you mean just put a T flip-flop on any old signal you won't get a 50% duty cycle unless by chance the triggering edges happen to be exactly in phase with a 50% duty cycle at the desired frequency... So no in 99% of all cases. The reason behind the 200 MHz (or better yet 400 MHz) would be to much much finer step granularity and not require advanced odd-number dividers (to yield 50% duty cycle). 50 MHz will net you only a few steps that will work: 50/2 = way too fast 50/3 = ~200% oc (difficult to design) 50/4 = ~50% oc 50/5 = ~25% oc (difficult to design) 50/6 = ~stock 50/7 = ~10% uc (difficult to design) 50/8 = ~20% uc 50/9 = ~30% uc (difficult to design) etc Something probably to look at in the future is the phase accumulator. This simple concept will effectively let you create ANY smaller frequency from any larger one but with a wobbly phase/duty cycle. If you never let the on/off period (wave's crest/trough) fall below your minimum it will be suitable for a Game Boy. Normally you can't use phase accumulators to drive anything video because the phase wobble upsets the display's ability to sync and analog pixels are also wobbly, but the Game Boy has a digital screen.
Underclock proof video http://www.youtube.com/watch?v=-Tt9X4Gx3f4 Thanks Calpis! Extremely helpful!! HUGE THANKS BUDDY!!! Sorry mikeryan. Bad_Ad84 is not a hater. But thanks for your help too!
