I've got my regs configured as: so the addresses are as follows: For a 64x32 tile display mode, one scroll plane should require 2048 words, so that's a chunk spare in between 0xD000 and 0xE000. It's not possible to configure the VDP so that Plane A's table is at 0xD000, as far as I know, so with the Window plane disabled this seems like a hole which can be used as tile space (should be able to fit 128 in there). I've thrown some tiles in there to see what happens and everything seems to be in order; the tiles show up, nothing else seems to be affected. Am I being naive?
Correct, you can only set bit 13-15 of the address, so the only possibilities are 0x0000, 0x2000, 0x4000, 0x6000, 0x8000, 0xA000, 0xC000 and 0xE000. Nope, it's very common for games to use "gaps" in VRAM for additional tiles / patterns.
