Looks like a nightmare to develop for and I am sure development times will increase, the standard core for the next gen systems(quad PPC in xbox2, single/multiple core for revolution) seems a lot easier to program for than the custom chain process in the cell. And we all remember all the bullshit hype over EE, and how EE would be more powerful than p4, and how it would be used in pcs, and how it wouldbe used to make movies. Funny how a P3 and nvidia chip in xbox make an EE ps2 look like absolute shit in graphics and performance. You can crank out great graphics on xbox almost instantly with the standard pc style components. To get close on ps2 requires all kinds of juggling with the memory and loads of time.
:boobies2 Assembler: my guess is that the amount of vector-based parallellism (sp) will be used in part for 3D math, video and audio tasks - so Sony might very well write a library to take care of that to "emulate" ASICs - i.e., something that runs on one or more APUs and receives commands from the PU/other APUs. Though seriously, I wonder how they're gonna make the APU RAM fast enough and keep it affordable at the same time. Moreover, cramming 8 cores onto a chip when they all use a 256 bit bus running at several Ghz will be a serious challenge. Also, the author does not mention anything about a pipelining/serialization scheme when using the Cell in "stream" mode - ie, there wouldnt be much point if one APU would be working at a time and the other 6 would lie dormant, they need to run in parallel otherwise there's not much point.
