PS3 concerns, cell architecture has very serious flaws

I was reading up on the CELL and RSX and came across a lot of
information that was pretty sensationalized on "the inquirer", so I decided to read up on my own and see what was true and not true.

I was not happy when I was done.



(image from inquirer)
Notice the upper right hand corner of the image. Yes, the on cpu memory
can only be accessed at under 16mb per second.

That's sony saying in the slide, officially "not a typo...."

Not really believing this I decided to read up on my own.

I remember and early demo I saw, and it was basically
approximated hardware based on sony specs. Now it's not even close
to the aimed performance, so no wonder you didn't see killzone. They
basically can't get that level of quality from the final specs.

Here's why, from an IBM whitepaper:

Bottlenecks

(SPE references one of the cores)




The SPEs on the north end of the chip are numbered 1357, and on the south are named 0246. Any communication between, say, SPE1 and SPE2 must "pass through" the CPU and the memory controller; transactions cannot go more than halfway around the EIB in a given direction. If a transaction would be too long clockwise, the communication must go counterclockwise instead, and vice versa. While truly an engineering marvel, EIB may find itself underachieving due to workload complexity. Another class of bottlenecks is contention. For instance, if four SPEs are trying to move data to or from the MIC at the same time, their aggregate bandwidth of 102.4GB/sec completely swamps the MIC's bandwidth of 25.6GB/sec. Similarly, while the SPEs are trying to interact with the MIC, the PPE may have degraded access to main memory. When a unit is overwhelmed, it might need to retry commands, which in turn slows traffic down even further.

Thus, balancing access is very important. Some tolerance is built in: the bus allows each element to have up to 64 outstanding requests, although individual units might have a shorter queue. The MIC can queue the full 64 requests, which is a long enough queue to give some insurance against clashes, and allow the MIC to optimize its use of the Rambus interface by reordering the commands when dependencies allow it.

--------------
So what does it mean?

It means that no more than three of the SPE's can talk to the memory controller at one time using full capacity. Four SPE's will fill the bus, and the CPU controller will not be able to access the memory at all.

To make things worse, if you want the idle processors to work together, they still have to access the cpu and mem controllers. This means you have to leave bandwidth for the cpu controller to access the mem controller, and the idle cpus to talk to each other via the cpu controller. So those three SPE's can't work at full capacity anyway.

What you can do is have all the SPE's work at the same time, but using
nowhere near the capacity they each have. Basically the PS3 gets punished
for performing well, and tweaking cell for better results in the future
seems to be a nightmare if not impossible.

Sony's offical response to the problem of slow and useless SPE memory
is: "Don't read from local memory, but write to main memory with RSX(tm) and read it from there instead"

This is the same main memory that only three SPE's going full capacity can read at once. Probably why the RSX chip also acts as a southbridge.

Why hasn't sony put an adequate memory controller in the CELL?
This is crippling to the whole design. If you look at the ibm design for
360 and for CELL, it's like some genius said, "let's just add more cpus dude!"

So what are we left with , if these are the final specs?

Crippling memory bottleneck that limits the cell to three SPE's working full capacity without drowning the bus. The XBOX 360 only has three cores on CPU. Unless something changes, the 360 has better memory access hands down.

GPU that at full speed is a little more than 1/2 the raw power of what is in 360
This is what could make or break the ps3.

Sony has four months to get this right, and even if the problems are resolved for production, the games being made right now are going to be
disappointing, look like first gen 360 games, and not show off the power of
the (hopefully) fixed cell design.

Sony faces an endless battle of microsoft exclusives versus sony exclusives, as these are the only games that will show off the hardware differences on the two platforms.

EA is not going to make kill themselves to have madden on ps3 look better. They will use common code and tweak for each console and you'll probably not be able to tell what game is on what system side by side.


Best case scenario:

Fix cell = 2x cpu power of 360
Fix rsx = Same GPU power of 360

Worst case scenario:

Cell not changed = Same cpu power as 360 with 2x the complexity
in memory usage.
RSX not fixed = 1/2 the graphical power of the 360.
Going up against 2nd or 3rd gen 360 games

This doesn't even take into account that Sony has no experience with
an xbox live type system, and the OS for the ps3 is an afterthough design hijacked off the PSX media device that is nearly three years old...

But the Japanese will buy it anyway, even if it is dog shit.
So ps3 is the hands down default winner, which is even funnier than the
cell memory architecture.

-ASSEMbler

 

The inspiration is inquirer, but I did some research to see if it was bullshit or not.

 

If we disregard the whole 16mb/s infos,

The main concern is still the SPE / BUS limitation listed in the white papers.

How many whitepapers list a bottleneck? The IBM 360 core has no such problems.

I made sure I didn't rely on the inquirer.

Check out the cell docs I posted, it's good reading.

 

If anything, it amounts to the ps3 being harder to program for with only 360 level return or slightly better for a lot more complexity.

 

I'm no technical genius either, but I can hope for the best for ps3. But when I read in the white papers that the cell has a bottleneck they can't get around.

I've asked some people about this and they say it's the least of their worries
compared to other problems and dealing with non final hardware.

 

And to think until unreal studios pretty much begged sony, they were going to put 256mb or ram in instad of 512mb

 

Exactly the problem.

You have to reserve bandwidth for the cpu PPE and memory controller to contact the spe units.

I dont know how much that will affect the system as you can poll all 7 of the spe units many many times pers second across the25gb per second bus.

however one will never get more than 40% or so capability out of each spe at the same time as three will saturate the bus alone, let alone reserved bandwidth for the PPE, the memory controller, and RSX data.

You cant even have two spe units work on something in the background on a maxed out mem bus as they require bandwidth to talk to each other via the ppe and the mem control.

Now the bus is very very fast, and you can juggle the spe units. But the 16mb a second access to the SPE on chip mem is slow enough to be useless. So you have the spe write to main ram and the rsx read from the main ram.

All I can say is that later generations of games are going to be a giant pain inthe ass to do.

The real question is if sony can pump out up-to-spec xdr-dram in only a few months.

If there's problems with the ram, I can't imagine the impact on ps3 performance.
Microsoft had it's share or problems with ddr3.

Man this system is going to be so last minute. they must have people working 24 hours a day in Japan on PS3.