So I`ve been looking through some docs (VDP2 manual is epic), schematics, and running a bit of code... they really went nuts didn`t they? Anyway, the main clock can run at 26.8 or 28.6MHz (for NTSC), and I guess a random read from SDRAM then takes two cycles, with page mode access taking one cycle. Is that right? What about VDP2 banked mode, are there any timing restrictions in setting up the cycle pattern registers? By drawing large, single-color polygons I was able to measure a fill rate of about 22Mpixels for VDP1 running at 26.8MHz. So I guess that under ideal conditions it can write one pixel per clock. Considering what the manual has to say about high-speed shrink mode, I assume that it normally loads every pixel of the texture even when it is not needed. So the pixel filling performance will drop when using a large texture to draw a smaller on-screen object? I have seen some conflicting info about the memory map. Is the SMPC accessed at $100000 or $5FC0000? (or both?) Can 32-bit SDRAM be accessed at $5900000? Is it correct that there is 1MB of 70ns 16-bit bus DRAM at $200000?
BIOS routines access the SMPC at $100000 (or rather, $20100000)... VDP1 under interlaced mode can be set to render only odd or only even lines during a particular field. This is sort of clever because one can take advantage of the higher vertical resolution in interlaced mode without needing twice the fill rate or twice the VRAM. The downside is that you must keep rendering at 60 fields/second because if you fall behind incomplete frames will be displayed. (Yabause doesn`t emulate this ability of VDP1 at all)
